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Caratteristiche 8641D
With each core having its own L2 cache, it can be particularly efficient when the two cores are running separate operating systems and data sharing is limited.
The device has dual 64 bit (72b with ECC) DDR2 memory controllers to match the bandwidth requirements of the two cores.The memory controllers can be assigned to each core for increased OS isolation[...]
The MPC8641D supports flexible software implementations: symmetric multiprocessing (SMP) and Asymmetric multiprocessing.[...]
With Asymmetric multiprocessing, two instances of the same operating system or two entirely separate operating systems can be run on the two cores, largely unaware of each other.
